In-line apparatus and method for manufacturing double-sided stacked multi-chip packages

ABSTRACT

Provided are in-line semiconductor chip packaging apparatuses that include a buffer assembly in which a reversing unit rotates a lead frame 180° between die attaching and/or wire bonding operations and methods of manufacturing an integrated circuit chip package using such an in-line integrated circuit chip packaging apparatus. Between packaging process operations, the lead frame, which includes first and second surfaces may be rotated, thereby reversing the orientation of the first and second surfaces. The apparatuses will include one or more processing units for attaching semiconductor chips to the leadframe, or a previously mounted semiconductor chip, or for forming wire bonds between the attached semiconductor chip(s) and the corresponding lead fingers of the lead frame, attached to and/or separated by an in-line buffer assembly that includes a reversing unit.

BACKGROUND OF THE INVENTION

This application claims priority from Korean Patent Application No.2003-44252, which was filed on Jul. 1, 2003, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirety by reference.

1. Field of the Invention

The present invention relates to an in-line integrated circuit chippackaging apparatus and a method for manufacturing in-line integratedcircuit chip packages and, more particularly, to an in-line integratedcircuit chip packaging apparatus for manufacturing a double-sidedstacked multi-chip packages using wire bonding techniques and a methodof manufacturing integrated circuit chip packages using the same.

2. Description of the Related Art

The continuing demand for improvements in mobile phones and otherpersonal electronics such as PDAs,MP3 players, digital cameras andnotebook computers, has resulting in a corresponding demand forelectronic devices that are smaller, lighter, higher capacity and morehighly integrated. One method of achieving these requirements involvesloading several integrated circuit chips onto a single electronic deviceusing a multi-chip packaging technique. Multi-chip packaging techniques,which produce a single package containing a plurality of individualintegrated circuit chips, reduces the size and weight of an electronicdevice as well as the area required to mount the semiconductor chipswithin the electronic device.

In a conventional integrated circuit chip packaging process, a leadframe is used for providing electrical connections between thesemiconductor chip and an external device. The lead frame is typicallymanufactured as a strip configured for packaging 8 or 16 semiconductorchips simultaneously.

One multi-chip packaging technique, the stack type loading method,involves loading a plurality of semiconductor chips on both faces of thelead frame. Other multi-chip packaging techniques include both the dualdie package (DDP) method which involves stacking of two semiconductorchips, one chip on each face of the lead frame, and the quad die package(QDP) method, which involves stacking four chips, two chips on eachface, on the lead frame.

FIG. 1 is a cross-sectional view of a conventional DDP 10. Asillustrated in FIG. 1, a conventional DDP 10 typically includes a firstsemiconductor chip 11 and a second semiconductor chip 13, which aremounted on a lead frame 20 that includes a die pad 21 and a lead finger23. The first semiconductor chip 11 and the second semiconductor chip 13are attached on an upper face and a lower face of the die pad 21 using afirst bonding layer 25 and a second bonding layer 26, respectively. Thefirst semiconductor chip 11 is electrically connected to the lead finger23 via a wire bond 27, and the second semiconductor chip 13 iselectrically connected to the lead finger 23 via a wire bond 28. Thefirst semiconductor chip 11, the second semiconductor chip 13, and thewire bonds 27 and 28 are protected from an external environment by aplastic molding 31, which is formed from a material such as an epoxymolding compound, which encapsulates and seals the more sensitiveportions of the structure.

FIG. 2 is a cross-sectional view of a typical QDP structure. Asillustrated in FIG. 2, a conventional QDP 30 includes four semiconductorchips 31, 33, 35, and 37, which are loaded on a lead frame 40 thatincludes a die pad 41 and a lead finger 43. During the manufacture of aconventional QDP according to FIG. 2, the first and second semiconductorchips 31, 33 are sequentially attached to an upper face of the die pad41 using first and second bonding layers 45, 47 respectively. Similarly,the third and fourth semiconductor chips 35, 37 will be sequentiallyattached to a lower face of the die pad 41 using third and fourthbonding layers 46, 48. The first semiconductor chip 31 may then beelectrically connected to the lead finger 43 using bonding wires 51 andthe second semiconductor chip 33 may be electrically connected to thelead finger using bonding wires 53. Similarly, the third semiconductorchip 35 may be electrically connected to the lead finger 43 usingbonding wires 55 and the fourth semiconductor chip 37 may beelectrically connected to the lead finger 43 using bonding wires 57.

The four semiconductor chips 31, 33, 35, 37, the corresponding bondingwires 51, 53, 55, and 57, and the bonding regions of the chips and thelead fingers may then be sealed in a plastic molding 61 formed from amaterial such as an epoxy mold compound (EMC) or other suitablecomposition.

A method of manufacturing a conventional integrated circuit chippackages such as the DDP and the QDP configurations depicted in FIGS. 1and 2 typically includes a die attach process for attaching anindividual semiconductor chip that has been separated from a wafer tothe lead frame or a semiconductor chip that has been previously mountedon the lead frame. A wire bonding process is then used for establishingelectrical connections between the semiconductor chip and the lead frameusing conductive metal wires. A molding process is then utilized toencapsulate and protect the semiconductor chips, bonding wires and innerportions of the lead frame in a molding resin to protect againstenvironmental contamination or mechanical damage, followed by atrim/form process for cutting and/or bending the exterior portion of thelead finger to obtain a desired lead configuration. Once the individualpackages have been completed, they may be subjected to somepost-assembly functional, parametric and/or accelerated life testing toevaluate the yield of the assembly process and the reliability of theresulting semiconductor chip packages. Because two semiconductor chips,for DDPs, or four semiconductor chips, for QDPs, are combined in asingle package, both the overall area within the electronic device andthe mounting area(s) on the circuit substrate can be decreased.Therefore, electronic devices that utilize these techniques andconfigurations can achieve an improved degree of miniaturization andincrease density.

However, conventional apparatuses for manufacturing an integratedcircuit chip package typically utilize separate processes and distinctpieces of equipment for the various die attaching, wire bonding andadhesive curing steps. Therefore, when manufacturing a DDP or QDP usinga conventional integrated circuit chip package apparatus, an operatormust sequentially load the lead frame into and unload the lead frame thedie attaching unit, the wire bonding unit, and the curing oven for eachsemiconductor chip that will be attached to the lead frame. For example,in manufacturing a DDP such as that depicted in FIG. 1, an operator musttypically manually transfer the lead frame at least five times since theprocesses of attaching, oven curing and chip bonding must each be donetwice. Similarly, in manufacturing a QDP such as that depicted in FIG.2, an operator must typically manually transfer the lead frame at leasteleven times over the course of performing each of the processes fourtimes in order to mount all four chips.

Therefore, the conventional method of manufacturing multi-chipintegrated circuit chip package process is complex, tends to requirerepeated operator intervention, much of which involves transferring thelead frames of the partially completed devices between variousapparatus, and is time-consuming. The convention methods and apparatus,therefore, tend to decrease productivity.

SUMMARY OF THE INVENTION

The exemplary embodiments of the present invention provide in-lineintegrated circuit chip packaging apparatuses that can be used tosimplify the packaging process and reduce the need for operatorinvolvement during the manufacture of doubled-sided stack multi-chippackages.

The exemplary embodiments of the present invention also provide methodsfor manufacturing integrated circuit chip packages that can reduce theassociated labor and process times and thereby increase productivity bysimplifying the manufacturing process for doubled-sided stack multi-chippackages.

According to one exemplary embodiment of the present invention, anin-line integrated circuit chip packaging apparatus comprises a loadingunit which supplies a lead frame having a first surface and a secondsurface opposite the first surface from a supply magazine containing thelead frame, a first package fabricating unit which performs theoperations required to attach a first semiconductor chip to the firstsurface of the lead frame, a second package fabricating unit whichattaches a second semiconductor chip to the second surface of the leadframe, and an unloading unit which unloads the lead frame from thesecond package fabricating unit and fills a receiving magazine. Abuffer, interposed between the first package fabricating unit and thesecond package fabricating unit, includes a reversing unit which rotatesthe lead frame so that the second surface, that was initially directeddownward, is fed into the second package fabricating unit directedupward.

The buffer includes a guide rail which guides the lead frame in a firstdirection, a driving shaft, which can extend perpendicularly to thefirst direction, mounted on a side of the guide rail, and a drivingmotor which supplies driving power to the driving shaft to rotate theguide rail a predetermined angle about an axis of the driving shaft.

The reversing unit may also include a fixing unit which supports andholds the lead frame so that the lead frame does not derail when theguide rail is rotated about the axis of the driving shaft. The guiderail supports at least one lead frame strip that will be reversed duringeach rotation by the reversing unit. The driving unit may supply drivingpower to the driving shaft using an air cylinder.

The buffer also includes both a first lead frame conveyor, that conveysthe lead frame from the first package fabricating unit to the reversingunit, and a second lead frame conveyor that conveys the lead frame tothe second package fabricating unit.

The first lead frame conveyor and the second lead frame conveyor mayinclude a pusher, operated by a cylinder, that pushes the lead frame toa next stage. A pusher operated by an air cylinder may be used to pushthe lead frames one by one from the magazine to the first packagefabricating unit can be installed in the loading unit.

The first and second package fabricating units can include die attachingunits that attach semiconductor chips to the lead frame and/or wirebonding units that electrically connects the semiconductor chip attachedto the lead frame to the lead frame.

According to another embodiment of the present invention, an in-lineintegrated circuit chip packaging apparatus includes a loading unitwhich supplies a lead frame having a first surface and a second surfaceopposite the first surface from a supply magazine holding the leadframe, a first die attaching unit, which attaches a first semiconductorchip on the first surface of the lead frame, a second die attachingunit, which attaches a second semiconductor chip on the second surfaceof the lead frame, a buffer, interposed between the first die attachingunit and the second die attaching unit, that includes a reversing unitwhich rotates the lead frame so that the orientation of the first andsecond surfaces is reversed before the lead frame is supplied to thesecond package fabricating unit, and an unloading unit which unloads thelead frame from the second package fabricating unit to a receivingmagazine.

According to a still another embodiment of the present invention, anin-line integrated circuit chip packaging apparatus includes a loadingunit which supplies a lead frame having a first surface and a secondsurface opposite the first surface from a supply magazine holding thelead frame, a first bonding unit which electrically connects a firstsemiconductor chip attached to the first surface of the lead frame tothe lead frame by wire bonding, a second wire bonding unit whichelectrically connects the second semiconductor chip attached to thesecond surface of the lead frame to the lead frame by wire bonding, abuffer, interposed between the first wire bonding unit and the secondwire bonding unit, that includes a reversing unit which rotates the leadframe so that the orientation of the first and second surfaces isreversed before the lead frame is supplied to the second packagefabricating unit, and an unloading unit which unloads the lead framefrom the second package fabricating unit to a receiving magazine.

According to a yet another embodiment of the present invention, anin-line integrated circuit chip packaging apparatus including a loadingunit which supplies a lead frame having a first surface and a secondsurface opposite the first surface from a supply magazine holding thelead frame, a package fabricating unit which performs a process requiredto attach a semiconductor chip to the upward facing surface of the leadframe, an unloading unit which unloads the lead frame from the packagefabricating unit to a receiving magazine, a buffer, disposed between thepackage fabricating unit and the unloading unit, which conveys the leadframe selectively to one of the package fabricating unit and theunloading unit depending on the state of the lead frame unloaded fromthe package fabricating unit, and a reversing unit, which rotates thelead frame so that both the first and the second surfaces of the leadframe may be directed upward before being returned to the packagefabricating unit. The apparatus may be configured and/or operated sothat the lead frame conveyor returns the lead frame to the packagefabricating unit only once after the reversing unit rotates the leadframe.

According to yet another embodiment of the present invention, anintegrated circuit chip package may be manufactured by loading a leadframe including a die pad having a first surface and a second surfaceopposite the first surface and a lead finger into a first die attachingunit oriented so that the first surface of the die pad is directedupward, attaching a first semiconductor chip to the first surface of thedie pad in the first die attaching unit, rotating the lead frame in thereversing unit, to which the first semiconductor chip has been attached,so that the second surface of the die pad is directed upward, the firstdie attaching unit, the reversing unit and the second die attaching unithaving an in-line, loading the lead frame into the second attachingunit, and attaching a second semiconductor chip to the second surface ofthe die pad in the second die attaching unit.

An adhesive tape, such as an UV tape, may be used to attach the firstsemiconductor chip and the second semiconductor chip to the die pad. Afirst heat or UV treatment to cure the adhesive tape used to bond thefirst and the second semiconductor chips to the first and second facesof the lead frame may be performed after both chips are attached. A wirebonding process may then be performed to form electrical connectionsbetween the first and second semiconductor chips and the lead fingersafter the adhesive tape has been cured. The wire bonding processtypically includes forming a series of first wire bonds thatelectrically connect the first semiconductor chip to the lead fingers,rotating the lead frame so that the second surface is directed upward,and forming a series of second wire bonds that electrically connect thesecond semiconductor chip to the lead fingers.

The method can further include attaching a third semiconductor chip tothe first semiconductor chip in the first die attaching unit, rotatingthe lead frame so that the second surface of the die pad is directedupward using the reversing unit, loading the lead frame in the seconddie attaching unit so that the second surface of the die pad is directedupward, and attaching a fourth semiconductor chip to the secondsemiconductor chip in the second die attaching unit. An adhesive tape,such as an UV tape, may be used to attach the third and fourthsemiconductor chips to the previously attached first and secondsemiconductor chips, respectively. A second heat or UV treatment may beperformed to cure the adhesive tape used for attaching the third and thefourth semiconductor chips to the first and the second semiconductorchips.

The method will also typically include a wire bonding process forelectrically connecting the third semiconductor chip and the fourthsemiconductor chip to the lead fingers after the second adhesive tapecuring treatment. The wire bonding process includes forming a thirdseries of wire bonds that electrically connect the third semiconductorchip to the lead fingers, rotating the lead frame so that the secondsurface is directed upward, and forming a fourth series of wire bondsthat electrically connect the fourth semiconductor chip to the leadfingers.

According to another embodiment of the present invention, an integratedcircuit chip package may be manufactured using a wire bonding process toform electrical connections between the first and a second semiconductorchips and the lead fingers of a lead frame, which includes a die padhaving a first surface and a second surface opposite the first surface,on which the first and the second semiconductor chip are attached, themethod comprising forming a first series of wire bonds that electricallyconnect the first semiconductor chip to the lead fingers in a first wirebonding unit, rotating the lead frame on which the first wire bonds havebeen formed so that the second surface of the die pad is directed upwardusing a reversing unit which is connected in-line with the first wirebonding unit, and forming a second series of wire bonds thatelectrically connect the second semiconductor chip to the lead fingersusing a second wire bonding unit which is connected in-line with thereversing unit.

The in-line integrated circuit chip packaging apparatus according to theexemplary embodiments of the present invention, can simplify thepackaging process, reduce the amount of handling by an operator duringthe packaging operation and reduce the turn around time (TAT), therebytending to increase the productivity of the integrated circuit chippackaging process.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail certain exemplaryembodiments thereof with reference to the attached drawings in which:

FIG. 1 is a cross-sectional view of a structure of a conventional dualdie package (DDP);

FIG. 2 is a cross-sectional view of a structure of a conventional quaddie package (QDP);

FIG. 3 is a block diagram illustrating an in-line integrated circuitchip packaging apparatus according to an exemplary embodiment of thepresent invention;

FIG. 4 is a illustration of an in-line integrated circuit chip packagingapparatus composing a wire bonding unit according to an exemplaryembodiment of the present invention;

FIG. 5A is a schematic diagram of a configuration of a reversing unit ofthe in-line integrated circuit chip packaging apparatus according to anexemplary embodiment of the present invention;

FIG. 5B is a cross-sectional view taken along a line VB-VB′ in FIG. 5A.

FIG. 6 is a schematic diagram of a pusher that may be used in thein-line integrated circuit chip packaging apparatus according to theexemplary embodiment of the present invention;

FIG. 7 is a block diagram illustrating an in-line integrated circuitchip packaging apparatus according to a second exemplary embodiment ofthe present invention;

FIG. 8 is a schematic view of the in-line integrated circuit chippackaging apparatus including a wire bonding unit according to a secondexemplary embodiment of the present invention;

FIGS. 9A-9G are cross-sectional views illustrating a method ofmanufacturing an integrated circuit chip package according to a firstexemplary embodiment of the present invention; and

FIGS. 10A-10G are cross-sectional views illustrating a method ofmanufacturing an integrated circuit chip package according to a secondexemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The present invention will be described more fully with reference to theaccompanying drawings, in which exemplary embodiments of the inventionare shown. It should be understood, however, that exemplary embodimentsof the present invention described herein can be modified in form anddetail without departing from the spirit and scope of the invention.Accordingly, the exemplary embodiments described herein are provided byway of example and not of limitation, and the scope of the presentinvention is not restricted to the particular embodiments describedherein.

FIG. 3 is a block diagram illustrating an in-line integrated circuitchip packaging apparatus according to a first exemplary embodiment ofthe present invention. Referring to FIG. 3, an exemplary in-lineintegrated circuit chip packaging apparatus 100 includes a loading unit110 to which a lead frame is supplied in a supply magazine, and firstand second package fabricating units 120 and 130 that performpredetermined processes for attaching semiconductor chips to the leadframes supplied from the loading unit 110. The first and second packagefabricating units 120 and 130 can respectively perform, for example, dieattaching processes for attaching semiconductor chips onto the leadframe and/or wire bonding processes for electrically connecting thesemiconductor chips to the lead frame using bonding wires. The first andsecond package fabricating units 120 and 130 are connected through abuffer 140 disposed there between. After fabrication is complete, thelead frame is unloaded from the second package fabricating unit 130 byan unloading unit 180 and transferred to a receiving magazine.

The buffer 140 includes a reversing unit 150 that reverses the leadframe orientation by rotating the lead frame 180° so that a surface ofthe lead frame that initially faces upward will be facing downwardbefore transferring the lead frame to the second fabricating unit 130.The buffer 140 also comprises a first lead frame conveyor 160 thatconveys the lead frame from the first package fabricating unit 120 tothe reversing unit 150, and a second lead frame conveyor 170 thatconveys the lead frame from the reversing unit 150 to the second packagefabricating unit 130.FIG. 4 illustrates first and second packagefabricating units 120 and 130 that include wire bonding units 122 and124, respectively. FIG. 4 illustrates a configuration including wirebonding units, but these can be replaced by or supplemented with dieattaching units as required.

FIGS. 5A and 5B are schematic diagrams of a portion of the reversingunit 150. FIG. 5A is a top view of the reversing unit 150 and FIG. 5B isa cross-sectional view taken along a line VB-VB′ in FIG. 5A. Referringto FIGS. 5A and 5B, the reversing unit 150 includes a guide rail 152that guides that movement of the lead frame L/F received from the firstpackage fabricating unit 120 through the first lead frame conveyor 160in a constant direction, i.e., an X direction. The guide rail 152 canalso be designed and configured to divert the movement of the lead framein either X direction and/or Y direction as required. The guide rail 152supports at least one lead frame strip while it is being reversed by thereversing unit 150.

A driving shaft 154 is mounted adjacent to the guide rail 152 andextends in the Y direction, i.e., perpendicular to the X direction. Adriving motor 156 may be used to rotate the guide rail 152 in apredetermined angular direction about an axis of the driving shaft 154,and is connected to the driving shaft 154 through a coupling 158. Whenthe driving shaft 154 is rotated by the driving motor 156, the guiderail 152 rotates 180° about the axis of the driving shaft 154. Thedriving motor 156 may supply power to the driving shaft 154 via an aircylinder (not shown) and may provide a smooth reversing motion as theguide rail 152 is rotating 180°. The reversing direction of the guiderail 152 can be controlled as required, that is, the reversing directioncan be clockwise or counter clockwise about the axis of the drivingshaft 154. The angular speed of the lead frame may also be varied toprovide a slow “soft” landing of the guide rail without unduly slowingthe reversing process. A fixing unit 159 mounted on the reversing unit150 may be used to hold or otherwise fix the position of the lead frameL/F relative to the guide rail 152 as the guide rail is being reversed.

FIG. 6 illustrates a pusher 162 that can be mounted on the first andsecond lead frame conveyors 160, 170 in the buffer 140. The pusher 162may be used to push the lead frame to a next stage for processing. Thepusher 162 may be moved reciprocally along the direction A by operationof a cylinder 164. The pusher 162 can be mounted on one or both of thefirst lead frame conveyor 160 and the second lead frame conveyor 170 asrequired for lead frame movement. For example, the pusher 162 can beused to push a lead frame L/F conveyed by the first lead frame conveyor160 to the guide rail 152 of the reversing unit 150. The pusher 162 canalso be used to push a lead frame L/F to the second lead frame conveyor170 after the lead frame has been rotated 180° by operation of thereversing unit 150.

The pusher 162 can also be mounted on the loading unit 110. In such acase, a plurality of lead frames stored in the supply magazine can besupplied to the first package fabricating unit 120 one-by-one byindexing the supply magazine position with synchronized operation of apusher 162 mounted on the loading unit 110.

A process for manufacturing an in-line integrated circuit chip packageusing the in-line integrated circuit chip packaging apparatus 100 willnow be described. When a lead frame with a first surface and a secondsurface opposite the first surface is supplied to the first packagefabricating unit 120 from the loading unit 110, the first surface of thelead frame is directed upward.

In the first package fabricating unit 120, a die attach process and/or awire bonding process is performed on the first surface of the leadframe. Then, the lead frame is conveyed from the first packagefabricating unit 120 to the buffer 140. The first lead frame conveyor160 of the buffer 140 conveys the lead frame to the reversing unit 150.The reversing unit 150 rotates the lead frame by 180° so that the secondsurface of the lead frame is directed upward.

The reversed lead frame with the second face upward is then conveyed tothe second package fabricating unit 130 by the second lead frameconveyor 170. After performing a die attaching process and/or a wirebonding process on the second face of the lead frame in the secondpackage fabricating unit 130, the lead frame is unloaded from the secondpackage fabricating unit 130. The unloaded lead frame is loaded to areceiving magazine by the unloading unit 180.

FIG. 7 is a block diagram of an exemplary apparatus 200 formanufacturing an in-line integrated circuit chip package according to asecond embodiment of the present invention. Referring to FIG. 7, theapparatus 200 may include a loading unit 210 to which a lead frame issupplied from a supply magazine, a package fabricating unit 220, whichmounts a semiconductor chip on the lead frame supplied from the loadingunit 210 or the first lead frame conveyer 260, and an unloading unit 280which unloads the processed lead frame from the buffer 240 into areceiving magazine.

In the package fabricating unit 220, a die attaching process and/or wirebonding process can be performed. The package fabricating unit 220 andthe unloading unit 280 are arranged in-line with a buffer 240 disposedtherebetween. The buffer 240 selectively returns the lead frame to thepackage fabricating unit 220 or to the unloading unit 280 according tothe state of completion of the lead frame during the packaging process.The buffer 240 includes a reversing unit 250 that rotates the lead frameby 180° so that the orientation of the first and second surfaces may bereversed between processing steps within the package fabricating unit220. The buffer 240 also includes a first lead frame conveyor 260 thatconveys the lead frame between the package fabricating unit 220 and thereversing unit 250, and a second lead frame conveyor 270 that conveysthe lead frame between the reversing unit 250 and the unloading unit280.

The reversing unit 250, the first lead frame conveyor 260, and thesecond lead frame conveyor 270 may generally be configured and operatedas explained above with reference to the FIGS. 3, 5A, 5B, and 6.However, in this embodiment, the reversing unit selectively reverses thelead frame 180° according to the state of the lead frame as it isreceived from the package fabricating unit 220.

More specifically, when the lead frame is supplied from the loading unit210 to the package fabricating unit 220, the first surface of the leadframe is directed upward. After performing a die attaching processand/or a wire bonding process on the first face of the lead frame in thepackage fabricating unit 220, the lead frame is conveyed to thereversing unit 250 via the first lead frame conveyor 260. The reversingunit 250 rotates the lead frame 180° so that the second surface of thelead frame is directed upward. The lead frame is then conveyed back tothe package fabricating unit 220 via the first lead frame conveyor 260with the second surface directed upward. In the package fabricating unit220, a die attaching process and/or a wire bonding process is performedon the second face of the lead frame. The completed lead frame istransferred from the package fabricating unit 220 to the reversing unit250 by the first lead frame conveyor 260. The reversing unit 250,typically without reversing the lead frame, conveys the lead frame tothe second lead frame conveyor 270 after all of the desiredsemiconductor chips have been attached to the first and second surfacesof the lead frame within the package fabricating unit 220. Then, thelead frame is conveyed to the unloading unit 280 where the lead frame isplaced in a receiving magazine.

FIG. 8 is a schematic view of a package fabricating unit 220 including awire bonding unit 222. In FIG. 8, a wire bonding unit is illustrated,but the wire bonding unit can be replaced with or supplemented by a dieattaching unit as desired.

FIGS. 9A-9G are cross-sectional views illustrating a method ofmanufacturing an integrated circuit chip package according to a firstexemplary embodiment of the present invention. Hereinafter, a processfor manufacturing a DDP will be described. Referring to FIG. 9A, a leadframe 300 including a die pad 302 having a first surface 302 a and asecond surface 302 b on opposite sides of the die pad 302, and a leadfingers 304 formed is prepared.

In order to attach a semiconductor chip on each of the first surface 302a and the second surface 302 b of the die pad 302, the lead frame 300 isloaded into the exemplary in-line integrated circuit chip packagingapparatus 100 as depicted in FIG. 3. Alternatively, the exemplaryin-line integrated circuit chip packaging apparatus 200 as depicted inFIG. 7 may be used.

The frame 300 is loaded to the first fabricating unit 120 with the firstsurface 302 a directed upward. Then, a first semiconductor chip 320 isattached to the first surface 302 a of the die pad 302 in the firstfabricating unit 120 using an adhesive tape 312 made of a UV tape orother suitable material. The lead frame 300 is then conveyed to thebuffer 140 from the first fabricating unit 120, and conveyed to thereversing unit 150 by the first lead frame conveyor 160.

Referring to FIG. 9B, the lead frame 300 with the first semiconductorchip 320 attached on the first surface 302 a is rotated 180° by thereversing unit 150 so that the second surface 302 b of the die pad 302is directed upward. The lead frame 300 is then conveyed to the secondpackage fabricating unit 130 by the second lead frame conveyor 170.

Referring to FIG. 9C, a second semiconductor chip 330 is attached to thesecond surface 302 b of the die pad 302 using an adhesive tape 322 madeof a UV tape or other suitable material. Afterward, the lead frame 300is unloaded from the in-line integrated circuit chip packaging apparatus100 by the unloading unit 180.

Referring to FIG. 9D, the lead frame 300 having the first semiconductorchip 320 on the first face 302 a and the second semiconductor chip 330on the second face 302 b is then heat treated 332 in an oven in order tocure the adhesive tapes 312 and 322. The temperature of the oven may,for example, be maintained at 180° C. and the lead frames treated for apredetermined time, i.e., approximately 60 minutes, to obtain thedesired cure of the adhesive.

Referring to 9E, for performing a wire bonding process on the lead frame300 having the first semiconductor chip 320 on the first surface 302 aand the second semiconductor 330 on the second surface 302 b, theexemplary in-line integrated circuit chip packaging apparatus 100 asdepicted in FIG. 4 is used. Alternatively, the exemplary in-lineintegrated circuit chip packaging apparatus 200 as depicted in FIG. 8may be used.

The lead frame 300, the first surface 302 a of which is directed upward,is loaded to the first wire bonding unit 122 by a loading unit 110. Afirst series of bonding wires 342 that electrically connect the firstsemiconductor chip 320 and the lead fingers 304 may be formed in thefirst wire bonding unit 122. The lead frame 300 is then conveyed to thereversing unit 150 in the buffer 140 by the first lead frame conveyor160.

Referring to FIG. 9F, the lead frame 300 is rotated 180° using thereversing unit 150 so that the second surface 302 b of the die pad 302is directed upward. The lead frame 300 is then conveyed to the secondwire boding unit 124 by the second lead frame conveyor 170.

Referring to FIG. 9G, the lead frame 300, the second surface 302 b ofwhich is directed upward is placed in the second wire bonding unit 124.In this state, a second series of bonding wires 344 may be formed toconnect the second semiconductor chip 330 and the lead fingers 304.

The lead frame 300 is then unloaded by the unloading unit 180, and thefirst semiconductor chip 320, the second semiconductor chip 330, thefirst wire bond 342, and the second wire bond 344 are encapsulated in aplastic material such as an epoxy molding compound (EMC) using aconventional molding method to complete the formation of the DDP.

FIGS. 10A-10G are cross-sectional views illustrating a method ofmanufacturing an integrated circuit chip package according to a secondexemplary embodiment of the present invention in which a process formanufacturing a QDP will be described. Referring to 10A, a lead frame300 including a die pad 302 having a first surface 302 a and a secondsurface 302 b on opposite sides of the die pad 302, and lead fingers 304is prepared.

A first semiconductor chip 320 and a second semiconductor chip 330 areattached to the first surface 302 a and the second surface 302 b,respectively, using the method of manufacturing the DDP described abovewith reference to FIGS. 9A-9G. The first and the second semiconductorchips 320, 330 are then connected to lead fingers 304 using firstbonding wires 342 and second bonding wires 344, respectively.

Afterward, the lead frame 300 is loaded by a loader 110 to an exemplaryin-line integrated circuit chip packaging apparatus 100 that includes afirst package fabricating unit 120 and a second package fabricating unit130 as depicted in FIG. 3. The first and second packaging fabricatingunits 120 and 130 are die attaching units. Alternatively, the exemplaryin-line integrated circuit chip packaging apparatus 200 as depicted inFIG. 7 may be used.

The lead frame 300, the first surface 302 a of which is directed upward,is placed in the first package fabricating unit 120. In the firstpackage fabricating unit 120, a third semiconductor chip 360 is attachedto the first semiconductor chip 320, which is attached to the firstsurface 302 a of the die pad 302, using an adhesive tape 352 made ofpolyimide or other suitable material. The lead frame 300 is thenconveyed to the reversing unit 150 of the buffer 140 by the first leadframe conveyor 160.

Referring to FIG. 10B, the lead frame 300 is rotated 180° using thereversing unit 150 so that the second surface 302 b of the die pad 302is directed upward. The lead frame is then conveyed to the secondpackage fabricating unit 130 by the second lead frame conveyor 170.

Referring to FIG. 10C, the lead frame 300, the second surface 302 b ofwhich is directed upward, is placed in the second package fabricatingunit 130. In the second package fabricating unit 130, a fourthsemiconductor chip 370 is attached to the second semiconductor chip 330,which is attached to the second surface 302 b of the die pad 302, usingan adhesive tape 354 made of polyimide or other suitable material. Thelead frame is then unloaded from the exemplary in-line integratedcircuit chip packaging apparatus 100 by an unloading unit 180.

Referring to FIG. 10D, the lead frame 300 having the first semiconductorchip 320, the second semiconductor chip 330, the third semiconductorchip 360, and the fourth semiconductor chip 370 is then heat treated 372in an oven in order to cure the adhesive tapes 352 and 354. Thetemperature of the oven may be maintained at 180° C. and the heattreatment may have a duration of about 60 minutes to cure the adhesivetapes sufficiently. Those of ordinary skill in the art will appreciatethat the combination of curing time, curing temperature and appliedcuring energy may be adapted for a range of conventional adhesives.

Afterward, using the exemplary in-line integrated circuit chip packagingapparatus shown in FIG. 4, a wire bonding process for electricallyconnecting the third and fourth semiconductor chips 360, 370 to the leadfingers 304 is performed. For this bonding process, the exemplaryin-line integrated circuit chip packaging apparatus shown in FIG. 8 canalso be used. Referring to 10E, the lead frame 300, the first surface302 a of which is directed upward, is loaded in the first wire bondingunit 122 by the loading unit 110. A third series of bonding wires 382for electrically connecting the third semiconductor chip 360 to the leadfinger 304 may then be formed. The lead frame 300 is then conveyed tothe reversing unit 150 of the buffer 140 by the first lead frameconveyor 160.

Referring to FIG. 10F, the lead frame 300 is rotated 180° by thereversing unit 150 so that the second surface 302 b is directed upward.The lead frame 300 is conveyed to the second wire bonding unit 124 bythe second lead frame conveyor 170. Referring to FIG. 10G, the leadframe 300, the second surface 302 b of which is directed upward, isplaced in the second wire bonding unit 124. In this state, a fourthseries of bonding wires 384 may be formed to electrically connect thefourth semiconductor chip 370 to the lead fingers 304.

The lead frame 300 is unloaded from the second wire bonding unit 124 bythe unloading unit 180, and the first semiconductor chip 320, the secondsemiconductor chip 330, the third semiconductor chip 360, the fourthsemiconductor chip 370, the first bonding wires 342, the second bondingwires 344, the third bonding wires 382, and the fourth bonding wires 384are encapsulated in a plastic material such as an epoxy molding compound(EMC) using a conventional molding method. Then, the formation of a QDPis complete.

While methods of in-line integrated circuit chip packaging according toexemplary embodiments of the present invention have been described withrespect to the in-line integrated circuit packaging apparatus 100 andapparatus illustrated in FIG. 4, one skilled in the art would understandhow to adapt and perform these methods using the in-line integratedcircuit chip packaging apparatus 200 and the apparatus illustrated inFIG. 8.

As described above, the in-line integrated circuit chip packagingapparatus according to the exemplary embodiments of the presentinvention include a buffer assembly or buffer that connects a first andthe second package fabricating units which are each composed of a dieattaching unit and/or a wire bonding unit, with the buffer interposedbetween the first and the second package fabricating units including areversing unit that rotates a lead frame by 180°. Manual handling of thelead frames by operators is reduced because the exemplary processes forattaching semiconductor chips on the surfaces of the lead frame andelectrically connecting the semiconductor chips to the lead frame areperformed using an exemplary in-line apparatus.

For example, when manufacturing a conventional DDP, the number of timesmanual handling is required for an attaching process, a curing process,and a wiring process can be reduced from the five typically required inthe conventional process to two, and when manufacturing a conventionalQDP, the manual handling can be reduced from eleven typically requiredin the conventional process to the five or fewer handling steps requiredby the exemplary apparatus and method according to the presentinvention.

According to the exemplary embodiment of the present invention,therefore, the number of manual operations and the turn around time(TAT) can both be reduced by simplifying the doubled-sided stackmulti-chip packaging process, thereby increasing the productivity of theintegrated circuit chip packaging process.

While this invention has been particularly shown and described withreference to certain exemplary embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the invention as defined by the appended claims.

1-12. (canceled)
 13. A method of manufacturing a double-sidedsemiconductor chip package comprising: preparing a lead frame having adie pad and leads terminating adjacent the die pad, the die pad having afirst surface and a second surface; orienting the lead frame with thefirst surface facing upwardly; feeding the lead frame into a firstprocessing unit wherein a first chip packaging operation is applied tothe first surface to obtain a processed lead frame; reversing theprocessed lead frame whereby the second surface is oriented to faceupwardly to obtain a reversed lead frame; and feeding the reversed leadframe into a second processing unit wherein a second chip packagingoperation is applied to the second surface to obtain a completed leadframe.
 14. A method of manufacturing a double-sided semiconductor chippackage according to claim 13, wherein: the first chip packagingoperation includes attaching a first semiconductor chip to the firstsurface of the die pad; and the second chip packaging operation includesattaching a second semiconductor chip to the second surface of the diepad.
 15. A method of manufacturing a double-sided semiconductor chippackage according to claim 13, wherein: the first chip packagingoperation includes forming wire bonds between a first semiconductor chipand the adjacent leads; and the second chip packaging operation includesforming wire bonds between a second semiconductor chip and the adjacentleads.
 16. A method of manufacturing a double-sided semiconductor chippackage according to claim 13, wherein: reversing the processed leadframe includes moving the processed lead frame onto a guide rail;rotating the guide rail 180° to obtain a reversed lead frame; andremoving the reversed lead frame from the guide rail.
 17. A method ofmanufacturing a double-sided semiconductor chip package according toclaim 16, wherein: the guide rail has a longitudinal axis and the guiderail is rotated about an axis that is perpendicular to the longitudinalaxis.
 18. A method of manufacturing a double-sided semiconductor chippackage according to claim 16, wherein: the guide rail has alongitudinal axis and the guide rail is rotated about an axis that isparallel to the longitudinal axis.
 19. A method of manufacturing adouble-sided semiconductor chip package comprising: preparing a leadframe having a die pad and leads terminating adjacent the die pad, thedie pad having a first surface and a second surface, the second surfacebeing positioned opposite the first surface; orienting the lead framewith the first surface facing upwardly; feeding the lead frame into aprocessing unit wherein a first chip packaging operation is applied tothe first surface to obtain a processed lead frame; reversing theprocessed lead frame whereby the second surface is oriented to faceupwardly to obtain a reversed lead frame; and returning the reversedlead frame to the processing unit wherein a second chip packagingoperation is applied to the second surface to obtain a completed leadframe.
 20. A method of manufacturing a double-sided semiconductor chippackage according to claim 19, wherein: the first chip packagingoperation includes attaching a first semiconductor chip to the firstsurface of the die pad or forming wire bonds between a firstsemiconductor chip and the adjacent leads; and the second chip packagingoperation includes attaching a second semiconductor chip to the secondsurface of the die pad or forming wire bonds between a secondsemiconductor chip and the adjacent leads.